What Signal Integrity Engineers Actually Do (And Why They're Always Tired)

May 10, 2026

What Signal Integrity Engineers Actually Do (And Why They're Always Tired)

You can spot one at a bench by the body language. Hunched over a 33-inch monitor, one hand on a touchscreen scope, the other hovering near a coffee that went cold four hours ago. There's a printout of a stackup taped to the wall with red pen all over it. Somebody on the schematic team thinks the board "should just work," and the SI engineer is staring down an eye that closed the moment the transmitter started running pre-emphasis. If you ask what they're doing, you'll get a long pause, then: "fighting the reference plane."

Signal integrity is one of those jobs that's invisible right up until it isn't. When it works, nobody knows you exist. When it fails, you're in a conference room at 11 p.m. explaining to four directors why a 1.6mm trace decided to act like an FM antenna. This is the work. This is why they're tired.

The Job Description Nobody Reads Correctly

If you ask a recruiter, a signal integrity engineer "ensures high-speed signals propagate cleanly across PCB traces and interconnects." That's the LinkedIn version. The actual job is closer to: prevent a 28 Gbps SerDes lane from turning your eight-layer board into a small radio station, while simultaneously convincing a layout designer that no, the differential pair cannot just "go around the BGA the long way."

The day-to-day breaks down something like this:

Pre-layout simulation. Running IBIS-AMI or HSPICE models before anyone's even routed the board, so you can tell mechanical engineering that their preferred connector placement is going to cost you 4 dB of insertion loss they don't have.
Stackup design. Arguing with the fab house about whether their "equivalent" 4.2 Dk laminate is actually 4.2 at 25 GHz (spoiler: it's not, and they don't have the Df data either).
Channel modeling. Building S-parameter blocks for every via, connector, package, and trace segment, then cascading them and watching your eye height drop with each addition until you're below mask.
Post-layout verification. Pulling the actual routed board, extracting the channel with a 3D solver, and discovering that the layout engineer routed a critical pair under a void in the reference plane because "there was space there."
Lab correlation. Sitting in front of a 70 GHz scope with a TDR, a VNA, and approximately seventeen calibration substrates, trying to reconcile why the measurement and the simulation disagree by 1.2 dB at the Nyquist.

That's the work. None of it is in the job description.

Why Everything Is an Antenna

There's a reason SI engineers develop a thousand-yard stare. At low frequencies, a wire is a wire. At 100 MHz, a wire is a transmission line. At 10 GHz, that same wire is a resonator, a coupler, a parasitic capacitor, an inductor, and yes, an antenna. The faster the edge rates climb, the more aggressively physics starts billing you for sins you didn't know you were committing.

A via stub you didn't back-drill? Quarter-wave resonator. A return path that crosses a split plane? Slot antenna. A length-matched pair where one side has three more vias than the other? Mode conversion factory. The list of ways to ruin a signal at modern data rates is functionally infinite, and every one of them is somebody's "small change to make routing easier."

This is why SI engineers talk about everything in terms of frequency content, not data rate. A 10 Gbps NRZ signal has meaningful energy out past 20 GHz. PAM4 at 56 Gbps? You're worrying about flatness to 40 GHz and beyond. The board doesn't care what protocol you think you're running. The board only knows how to behave like a distributed network at whatever frequencies you've decided to push through it.

The Eye Diagram As Diagnostic Tea Leaves

If you've never watched an SI engineer stare at an eye diagram, it looks a lot like a chess grandmaster reading a board. They're not just looking at whether it's open. They're reading the slope of the rising edge for ISI, checking the inner contour for jitter components, watching the crossing point for duty cycle distortion, scanning the corners for reflection echoes.

"There's a bump at 200 ps after the rising edge." That bump is a reflection off a connector launch. They know this because they've seen this exact bump on three different programs across two companies, and the fix is always the same: tighten the anti-pad, kill the stub, get the impedance discontinuity below 5 percent.

The eye is a compressed diagnostic image. Every defect on the channel writes itself into the eye somewhere. SI engineers learn to decompress it the way radiologists read MRIs. Then they go fix the channel, run the sim again, and find a new defect they didn't see before because the first one was masking it. This is sometimes called "peeling the onion." It is also sometimes called "why am I still here at 9 p.m."

The Cross-Functional Tax

Here's the part the job postings don't mention. An SI engineer is, structurally, the person who tells everybody else they can't do what they want to do.

Layout wants to route diagonally across the plane split. No.

Mechanical wants to move the connector 8 mm because of an enclosure tolerance. That moves the launch into a via field. No.

Power integrity wants to shrink the decoupling cap count to save BOM cost. Those caps are managing the AC return path for your high-speed channels. No.

The schematic engineer wants to add a 0-ohm jumper "just in case." That's a 2 mm impedance discontinuity. No.

The program manager wants to skip 3D extraction "because we did it last time and it was fine." Last time was 16 Gbps. This is 32. No.

Every "no" is a meeting. Every meeting is an explanation. Every explanation involves drawing field lines on a whiteboard for someone who hasn't thought about field lines since school. The cumulative cost of this — the diplomatic overhead of being the project's resident physics enforcer — is enormous. It is also entirely uncompensated.

The Lab Hours

Simulation is half the job. The other half is correlation, and correlation happens in the lab at hours that polite society does not work. There's a reason: the high-end equipment is shared. The 70 GHz scope, the 4-port VNA with the millimeter-wave extenders, the BERT — these are not on every bench. They're in a lab, on a sign-up sheet, and your slot is Thursday 7 p.m. to midnight.

You will spend those five hours doing a calibration that takes 90 minutes, taking a measurement that takes 20, and then spending the rest of the slot trying to figure out why your TDR shows a reflection at 47 ps that your sim doesn't predict. You will not figure it out by midnight. You will go home, dream about it, come back the next day, and discover it was a probe tip seating issue.

This is normal. This is the job. This is why the SI engineers in your building always look like they slept in the parking lot. Sometimes they did.

Q&A: Things People Ask

Is it actually that hard, or are SI engineers just dramatic?

Both. The work is genuinely difficult because the problems are non-intuitive and the toolchain is brutal. It is also true that anybody who has spent a decade explaining return paths to schematic engineers develops a certain theatrical flair when describing their suffering. The drama is earned.

Will AI take this job?

Eventually some of it. Pattern recognition on eye diagrams, parameter sweeps, layout DRC for high-speed rules — sure. But channel modeling at 112 Gbps PAM4 with multiple connector hops involves enough domain judgment that the bottleneck isn't the math. It's knowing which simplifying assumption is going to bite you. That's not going anywhere soon.

How do you know when a board is "done"?

You don't. You know when it passes compliance, hits the BER target with margin, and survives corner-lot units across temperature. You also know that "done" is a moving target because the next program is at a higher data rate, on a smaller stackup, with less power budget, and somebody already told the customer it'll be ready by Q3.

Why does everyone in this field drink so much coffee?

See: lab hours, cross-functional tax, eye diagrams that close on Friday afternoon.

The Quiet Part

The thing about signal integrity work is that the satisfaction is private. When a channel comes up clean — when the eye is wide open, the BER floor is below 10⁻¹⁵, the margin is generous, and the lab data matches the sim within half a dB — there is a quiet moment of professional pleasure that nobody else in the company is equipped to share. The layout engineer doesn't get it. The PM definitely doesn't get it. Your manager understands it abstractly. The only people who really get it are the other SI engineers, and they're in their own labs at 11 p.m. fighting their own reference planes.

So you take the win, log the data, write the report nobody will read in full, and go home. The board ships. Customers don't know your name. The product works because of decisions you made eighteen months ago about a stackup that nobody will ever look at again. And tomorrow there's a new channel, a new connector, a new fab vendor with a suspicious Dk number, and a new 11 p.m. lab slot with your name on it.

That's the job. Every wire is an antenna. Every plane has a slot. Every via has a stub. Somebody has to care about it, and that somebody is tired.